1. Technical Field
This disclosure relates to testing and repairing semiconductor memories and more particularly, to a system and method for efficiently calculating and analyzing redundancies for semiconductor memories for repairing the semiconductor memories.
2. Description of the Related Art
Testing and repairing semiconductor memories is an important part of providing high reliability and controlling the quality of semiconductor memory products. A typical back-end test flow for a dynamic random access memory (DRAM) device usually includes:
1) A Wafer-Test/Redundancy Calculation. This includes testing all memory cells on a chip to determine failures. Then, determining if the failures can be fixed by employing available redundancy elements.
2) Fusing. This includes fixing the defects by using redundant elements.
3) Burn-In Test. This includes a retest employing redundant memory cells to ensure proper functionality.
4) Final Component Test. This includes acceptance testing to ensure product quality.
5) Building of a Multichip Module. Most chips are employed on a board or module and are configured to include a plurality of chips. For example, Simm/Dimm/Rimm devices may be fabricated from two or more memory chips.
6) Module Test. The module is tested as a whole including solder joints, pins, etc. as well as the memory chips.
After fusing, however, a chip cannot be fixed anymore. This is detrimental for many reasons including:
1) Not all fails can be detected during wafer tests (for example, single cell failures (BLC and/or HT), word line failures (LPST), etc.).
2) Some additional fails will be introduced during packaging, burn in and building of the multichip module.
3) Additional parts will be lost due to excessive test guard band from wafer to component to module.
4) One fail on one component of a module results in scrapping the whole module, that is possibly 8 or 16 chips. (This is also one reason why testing is more intensive before building modules than after.)
Attempts have been made to address the problems described above. In U.S. Pat. No. 5,796,746 to W. M. Farnworth et al., entitled xe2x80x9cDevice and Method for Testing Integrated Circuit Device in an Integrated Circuit Module,xe2x80x9d concepts for repairing chips on modules are presented. The analysis aspect is handled in a tester where special pins (not connected [NC] pins according to JEDEC spec) are used for setting the electrical fuses.
Concepts for on chip fail bit map analysis (and consequently redundancy calculation) are presented in xe2x80x9cBuilt in Self Repair for Embedded High Density SRAM,xe2x80x9d by Ilyoung Kim et al., Bell Laboratories; Proceedings ITC 1998 and xe2x80x9cSemiconductor Manufacturing Process Monitoring Using Built-In Self-Test for Embedded Memories,xe2x80x9d by Ivo Schanstra et al., Philips Semiconductors; Proceedings ITC 1998. Both papers relate to SRAMs, and the concepts of these papers are limited to column redundancies.
Therefore, a need exists for a system and method for efficiently calculating and analyzing redundancies for semiconductor memories for repairing the semiconductor memories. A further need exists for repairing the semiconductor memories after packaging. A still further need exists for repairing multiple types of failures after packaging, e.g., column failures, row failures, cell failures, etc.
A method for analyzing failures for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region. It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered.
In other methods, the memory device may include one of a single memory chip and a packaged multichip module. The step of testing the at least one memory chip may include employing built in self testing. The components may include one of a single memory cell, a row and a column. The row and column may each include a plurality of devices, for example, wordline, bitlines, etc. The method may be performed on-chip on the at least one memory chip. The step of inputting the addresses of the failed components to the redundancy calculation region may include the steps of inputting the addresses of the failed components to comparators to compare the addresses of the failed components which are currently discovered to the previous failure addresses stored in accumulators. The step of determining if the at least one memory chip is fixable based on the new failures which have been discovered may be performed by accumulating a number of matches between failure addresses and stored failure addresses and comparing the number of matches to a threshold value such that a matching event which causes the number of matches to equal the threshold is employed to designate the address of components to be repaired.
Another method for analyzing failures for semiconductor memories includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region, and the redundancy calculation region is adapted to receive failure addresses of failed components. The redundancy calculation region includes comparators for comparing the failure addresses to previous failure addresses to determine if new failures have been discovered, a memory for selectively storing addresses of failures, and decision logic for determining if the memory device is fixable based on the new failures which have been discovered. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region by employing the comparators. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated, and a match count incremented. Otherwise, the failure address is stored in the redundancy calculation region. If the match count meets a threshold value, a must repair event is designated to repair the component using redundancies.
In other methods, the memory device may include one of a single memory chip and a packaged multichip module. The step of testing the at least one memory chip may include employing built in self testing. The components may include one of a single memory cell, a row and a column wherein the row and column may include a plurality of devices. The method may be performed on-chip on the at least one memory chip. The step of inputting the addresses of the failed components to the redundancy calculation region may include the steps of inputting the addresses of the failed components to the comparators to compare the addresses of the failed components which are currently discovered to the previous failure addresses stored in accumulators. The step of designating a must repair event may include the steps of accumulating a number of matches for between failure addresses and stored failure addresses and comparing the number of matches to a threshold value such that a matching event which causes the number of matches to equal the threshold is employed to designate the address of components to be repaired.
A system for analyzing failures for semiconductor memories, in accordance with the invention includes a self testing memory device including at least one memory chip adapted to determine failure addresses of failed components on the at least one memory chip. The at least one memory chip includes a redundancy calculation region. The redundancy calculation region is adapted to receive failure addresses of failed components. The redundancy calculation region also includes comparators for comparing the failure addresses to previous failure addresses to determine if new failures have been discovered, a memory for selectively storing addresses of failures, and decision logic for determining if the memory device is fixable based on the new failures which have been discovered.
In alternate embodiments, the memory device may include one of a single memory chip and a packaged multichip module. The at least one memory chip may include built in self testing. The components may include one of a single memory cell, a row and a column. The redundancy calculation region may include additional comparators to compare a number of matches between new failure addresses and previously stored failure addresses to a threshold value for designation a must-repair event. The redundancy calculation region may include adders to increment the number of matches when a match occurs. The at least one memory chip may include a plurality of redundancy calculation regions which are pipelined to store addresses of a plurality of failed components. The pipeline may include latches disposed between the redundancy calculation regions to provide synchronization therebetween.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.